Design of Digital Circuits with VHDL Programming

This course is part of Chip based VLSI design for Industrial Applications Specialization

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4 modules

Gain insight into a topic and learn the fundamentals.

20 reviews

Intermediate level

Recommended experience

2 weeks to complete

at 10 hours a week

Flexible schedule

Learn at your own pace

4 modules

Gain insight into a topic and learn the fundamentals.

20 reviews

Intermediate level

Recommended experience

2 weeks to complete

at 10 hours a week

Flexible schedule

Learn at your own pace

Skills you'll gain

Tools you'll learn

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Assessments

4 assignments

Taught in English

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This course is part of the Chip based VLSI design for Industrial Applications Specialization

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There are 4 modules in this course

This course is designed to provide a comprehensive understanding of digital circuit design using VHDL programming with Xilinx ISE. Participants will learn the fundamentals of VHDL, simulation modeling, and design methodologies for digital circuits, including combinational and sequential circuits. Practical exercises using Xilinx ISE will enhance hands-on skills in circuit implementation, simulation, and analysis.

This module provides a comprehensive introduction to VHDL (VHSIC Hardware Description Language) programming, focusing on digital circuit design and simulation. Participants will learn about VHDL design elements, data objects, modeling styles, delay type modeling, operators, concurrent statements, process statements, subprograms, data flow description, behavioral description, attributes, and logic operations. The module aims to simplify VHDL programming concepts and techniques, making it accessible for beginners and providing a strong foundation for digital circuit design using VHDL.

What's included

16 videos5 readings1 assignment

16 videos Total 120 minutes

About the Specialization 3 minutes
About the Course 5 minutes
Importance of VHDL Programming Language in Digital Design 10 minutes
VHDL Design and Modelling Styles - Part 1 4 minutes
VHDL Design and Modelling Styles - Part 2 10 minutes
Basic Design Elements of VHDL 8 minutes
VHDL - Object 9 minutes
Structural Description Using VHDL 10 minutes
VHDL - Configuration 10 minutes
VHDL - Operators and Process Statements 7 minutes
VHDL - Conditional Statements and Loops 10 minutes
Dataflow Description Using VHDL 6 minutes
Behavioral Description Using VHDL 8 minutes
Attributes in VHDL 8 minutes
VHDL Programming for Logic Operations - Part 1 5 minutes
VHDL Programming for Logic Operations - Part 2 6 minutes

5 readings Total 50 minutes

Specialization Reading 10 minutes
Course Reading 10 minutes
Course Glossary 10 minutes
VHDL - Data Types 10 minutes
VHDL - User Defined Data Types 10 minutes

1 assignment Total 30 minutes

Assessment on VHDL Programming Made Easy 30 minutes

This module provides a comprehensive exploration of digital combinational circuits design using VHDL programming within the Xilinx ISE Design Suite environment. Participants will delve into fundamental concepts such as AND gates, half adders, full adders, multiplexers, demultiplexers, encoders, decoders, comparators, barrel shifters, and binary-to-BCD and binary-to-Gray code converters. The module covers various VHDL modeling styles including structural, dataflow, and behavioral modeling, enabling a deep understanding of circuit design and simulation.

What's included

51 videos1 assignment

51 videos Total 455 minutes

Xilinx ISE Installation and its Design Flow - Part 1 8 minutes
Xilinx ISE Installation and its Design Flow - Part 2 7 minutes
Xilinx ISE Installation and its Design Flow - Part 3 11 minutes
Structural Modelling Style in VHDL with Half Adder - Part 1 9 minutes
Structural Modelling Style in VHDL with Half Adder - Part 2 8 minutes
Structural Modelling Style in VHDL with Half Adder - Part 3 8 minutes
Structural Modelling Style in VHDL with Half Adder - Part 4 8 minutes
Dataflow Modelling Style in VHDL with Half Adder - Part 1 9 minutes
Dataflow Modelling Style in VHDL with Half Adder - Part 2 8 minutes
Behavioral Modelling Style in VHDL with Half Adder - Part 1 10 minutes
Behavioral Modelling Style in VHDL with Half Adder - Part 2 8 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 1 14 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 2 10 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 3 7 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 4 8 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 5 8 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 6 7 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 7 11 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 1 13 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 2 9 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 3 9 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 4 6 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 5 8 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 6 7 minutes
Design of Multiplexer Using Various Modelling Styles in VHDL - Part 1 10 minutes
Design of Multiplexer Using Various Modelling Styles in VHDL - Part 2 10 minutes
Design of Multiplexer Using Various Modelling Styles in VHDL - Part 3 12 minutes
Design of Multiplexer Using Various Modelling Styles in VHDL - Part 4 8 minutes
Design of Multiplexer Using Various Modelling Styles in VHDL - Part 5 8 minutes
Design of Demultiplexer Using Various Modelling Styles in VHDL - Part 1 12 minutes
Design of Demultiplexer Using Various Modelling Styles in VHDL - Part 2 6 minutes
Design of Demultiplexer Using Various Modelling Styles in VHDL - Part 3 11 minutes
Design of Demultiplexer Using Various Modelling Styles in VHDL - Part 4 12 minutes
Design of Encoder Using Various Modelling Styles in VHDL - Part 1 9 minutes
Design of Encoder Using Various Modelling Styles in VHDL - Part 2 5 minutes
Design of Encoder Using Various Modelling Styles in VHDL - Part 3 9 minutes
Design of Encoder Using Various Modelling Styles in VHDL - Part 4 12 minutes
Design of Decoder Using Various Modelling Styles in VHDL - Part 1 12 minutes
Design of Decoder Using Various Modelling Styles in VHDL - Part 2 5 minutes
Design of Decoder Using Various Modelling Styles in VHDL - Part 3 10 minutes
Design of Decoder Using Various Modelling Styles in VHDL - Part 4 11 minutes
Design of 4-bit Comparator Using Various Modelling Styles in VHDL - Part 1 10 minutes
Design of 4-bit Comparator Using Various Modelling Styles in VHDL - Part 2 10 minutes
Design of 4-bit Comparator Using Various Modelling Styles in VHDL - Part 3 8 minutes
Design of 4-bit Comparator Using Various Modelling Styles in VHDL - Part 4 9 minutes
Design of 8-bit Barrel Shifter Using VHDL - Part 1 12 minutes
Design of 8-bit Barrel Shifter Using VHDL - Part 2 7 minutes
Design of 4-bit Binary to BCD Converter in VHDL - Part 1 8 minutes
Design of 4-bit Binary to BCD Converter in VHDL - Part 2 5 minutes
Design of 4-bit Binary to Grey Code Converter in VHDL - Part 1 7 minutes
Design of 4-bit Binary to Grey Code Converter in VHDL - Part 2 6 minutes

1 assignment Total 30 minutes

Assessment on Design of Digital Combinational Circuits with VHDL Programming Using Xilinx ISE 30 minutes

This module focuses on the design and implementation of digital sequential circuits using VHDL programming within the Xilinx ISE-I environment. Participants will delve into fundamental sequential circuit components such as D latch, D flip-flop, SR flip-flop, JK flip-flop, T flip-flop, shift registers, counters, and FIFO memories. Various VHDL modeling styles including structural, dataflow, and behavioral modeling will be utilized to develop and analyze the functionality of these sequential circuits.

What's included

20 videos1 assignment

20 videos Total 173 minutes

Design of D Latch Using Various Modelling Styles in VHDL - Part 1 10 minutes
Design of D Latch Using Various Modelling Styles in VHDL - Part 2 6 minutes
Design of D Latch Using Various Modelling Styles in VHDL - Part 3 10 minutes
Design of D Latch Using Various Modelling Styles in VHDL - Part 4 11 minutes
Design of D Flip Flop using VHDL 13 minutes
Design of SR Flip Flop using VHDL - Part 1 8 minutes
Design of SR Flip Flop using VHDL - Part 2 7 minutes
Design of JK Flip Flop using VHDL - Part 1 7 minutes
Design of JK Flip Flop using VHDL - Part 2 9 minutes
Design of T Flip Flop using VHDL 11 minutes
Design of 5-bit Shift Register Using VHDL Part 1 12 minutes
Design of 5-bit Shift Register Using VHDL Part 2 6 minutes
Design of Universal Shift Register using VHDL - Part 1 10 minutes
Design of Universal Shift Register Using VHDL - Part 2 9 minutes
Design of 4-bit Counter Using VHDL - Part 1 7 minutes
Design of 4-bit Counter Using VHDL - Part 2 6 minutes
Design of First in First Out (FIFO) Memory Using VHDL Part 1 7 minutes
Design of First in First Out (FIFO) Memory Using VHDL Part 2 6 minutes
Design of Asynchronous First in First Out (FIFO) Memory Using VHDL Part 1 11 minutes
Design of Asynchronous First in First Out (FIFO) Memory Using VHDL Part 2 6 minutes

1 assignment Total 30 minutes

Assessment on Design of Digital Sequential Circuits with VHDL Programming Using Xilinx ISE-I 30 minutes

This module delves into the design and implementation of digital sequential circuits using VHDL programming techniques within the Xilinx ISE-II environment. Participants will explore various sequential circuit components such as Single Port RAM, Dual Port RAM, sequence detectors (including Mealy and Moore machines), and a digital model of a vending machine. The module emphasizes hands-on learning, combining theoretical concepts with practical design and simulation exercises to develop a comprehensive understanding of digital sequential circuit design methodologies.

What's included

23 videos1 assignment

23 videos Total 182 minutes

Design of Single Port RAM using VHDL - Part 1 7 minutes
Design of Single Port RAM using VHDL - Part 2 8 minutes
Design of Dual Port RAM using VHDL - Part 1 7 minutes
Design of Dual Port RAM using VHDL - Part 2 9 minutes
Design of Mealy Non-overlapping 3-bit Sequence Detector using VHDL - Part 1 7 minutes
Design of Mealy Non-overlapping 3-bit Sequence Detector using VHDL - Part 2 7 minutes
Design of Mealy Non-overlapping 3-bit Sequence Detector using VHDL - Part 3 6 minutes
Design of Mealy Non-overlapping 5-bit Sequence Detector using VHDL - Part 1 11 minutes
Design of Mealy Non-overlapping 5-bit Sequence Detector using VHDL - Part 2 6 minutes
Design of Mealy Overlapping 3-bit Sequence Detector using VHDL - Part 1 9 minutes
Design of Mealy Overlapping 3-bit Sequence Detector using VHDL - Part 2 7 minutes
Design of Mealy Overlapping 5-bit Sequence Detector Using VHDL Part 1 10 minutes
Design of Mealy Overlapping 5-bit Sequence Detector Using VHDL Part 2 7 minutes
Design of Moore Non-overlapping 3-bit Sequence Detector Using VHDL Part 1 12 minutes
Design of Moore Non-overlapping 3-bit Sequence Detector Using VHDL Part 2 6 minutes
Design of Moore Non-overlapping 5-bit Sequence Detector using VHDL - Part 1 10 minutes
Design of Moore Non-overlapping 5-bit Sequence Detector using VHDL - Part 2 6 minutes
Design of Moore Overlapping 3-bit Sequence Detector Using VHDL Part 1 10 minutes
Design of Moore Overlapping 3-bit Sequence Detector Using VHDL Part 2 6 minutes
Design of Moore Overlapping 5-bit Sequence Detector using VHDL - Part 1 9 minutes
Design of Moore Overlapping 5-bit Sequence Detector using VHDL - Part 2 6 minutes
Design of Vending Machine Using VHDL Part 1 8 minutes
Design of Vending Machine Using VHDL Part 2 10 minutes

1 assignment Total 30 minutes

Assessment on Design of Digital Sequential Circuits with VHDL Programming Using Xilinx ISE-II 30 minutes

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L&T EduTech

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